This application is related to the following U.S. patent applications, which are filed on the same day as this application, and which have a common assignee and common inventors.
1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to a mechanism for randomly varying the frequency of an oscillator that is employed within an integrated circuit random number generator.
2. Description of the Related Art
Many present day computer-based applications rely heavily on the availability of random numbers. What has historically been the province of scientific programmers has more recently crept over into the commercial realm.
In prior years, large and powerful computing systems utilized random numbers for use within simulation programs to realistically model stochastic properties of phenomena of interest, such as the flow of traffic within a large network of computers.
And while the requirement for efficient and convenient generation of random numbers has not declined with respect to the modeling and simulation areas, because technological advances have provided more computing power to desktop computers in more recent years, such requirements have been imposed on the elements of desktop computers themselves. In fact, processing power increases in desktop computing have given rise to entirely new application areas that depend upon the generation of random numbers. For instance, random numbers are now widely used within many computer games to locate, say, asteroids or enemy fighters. To be acceptable to the consumer as a credible representation of reality, computer games must simulate their corresponding phenomena of interest in the same probabilistic fashion as one would expect such phenomena to occur in real life.
Another application area that depends upon the availability of random numbers is cryptography, an area that continues to provide very demanding criteria for random number generation. Within this field, random numbers are employed as cryptographic keys that are used by algorithms to encrypt and decrypt electronic files or streams of data for storage or transmission. For example, random keys are generated to encrypt financial data as secure electronic transactions are processed over the Internet. Remarkably, it is becoming more and more commonplace to find that ordinary electronic mail messages and the like are being encrypted for transmission between parties.
At present, most of the random number generation within desktop computing systems is accomplished within an application program. This form of generation is known as pseudo-random number generation because generation of the numbers employs a mathematical algorithm to produce a sequence of independent numbers that comport with a uniform probability distribution. Typically, a xe2x80x9cseedxe2x80x9d number is initially selected, then the algorithm proceeds to crank out numbers that appear to be random, but that are entirely deterministic in nature given knowledge of the seed. To be truly random, a random number generator must be based upon random attributes of some physical devices, such as the thermal noise generated across a diode or resistor.
Some hardware-based random number generators are available as separate integrated circuits, but to date, no hardware technique or approach exists that lends itself to incorporation within a microprocessor circuit. And since a microprocessor is the heart of any desktop computing system, it is advantageous for random numbers to be generated directly within the microprocessor itself.
Therefore, what is needed is a hardware-based random number generator that is easily incorporated into an integrated circuit design, and in particular, into the design of a present day microprocessor.
In addition, what is needed is a random number generation apparatus that utilizes logic elements which are common to those used within a microprocessor integrated circuit.
The present invention provides a superior technique hardware-based random number generation. In one embodiment, a frequency variation apparatus is provided for use in a random number generator. The frequency variation apparatus includes sampling frequency variation logic and a sampling frequency oscillator. The sampling frequency variation logic produces a noise signal that corresponds to parity of two independent and asynchronous oscillatory signals. The sampling frequency oscillator is coupled to the sampling frequency variation logic. The sampling frequency oscillator receives the noise signal, and varies a sampling frequency within the random number generator in accordance with the noise signal.
One aspect of the present invention contemplates a random number generation apparatus for use within an integrated circuit. The random number generation apparatus has a fast oscillator, a slow oscillator, and frequency variation logic. The fast oscillator generates a fast oscillatory signal at a first frequency. The slow oscillator generates a slow oscillatory signal at a second frequency, where the slow oscillatory signal is employed to take samples of the fast oscillatory signal to produce bits for a random number, and where the slow oscillator varies the second frequency according to a noise signal. The frequency variation logic is coupled to the slow oscillator. The frequency variation logic generates the noise signal, where the noise signal varies according to parity of two independent oscillatory signals.
Another aspect of the present invention comprehends a bit generation mechanism, for use in a random number generator. The bit generation mechanism includes a first oscillatory signal, a second oscillatory signal, synchronization logic, third and fourth oscillatory signals, and parity logic. The first oscillatory signal is generated by a first oscillator, and oscillates at a first frequency. The second oscillatory signal is generated by a second oscillator, and oscillates at a second frequency. The said second frequency varies according to a noise signal. The synchronization logic is coupled to the first and second oscillatory signals. The synchronization logic serially generates bits for a random number at a rate proportional to the second frequency. The third and fourth oscillatory signals independently oscillate at third and fourth frequencies. The parity logic is coupled to the third and fourth oscillatory signals. The parity logic generates the noise signal based upon parity of the third and fourth oscillatory signals.